Thermal-Aware SoC Macro Placement and Multi-chip Module Design Optimization with Bayesian Optimization-Reference-Cited by-同舟云学术

Thermal-Aware SoC Macro Placement and Multi-chip Module Design Optimization with Bayesian Optimization

Published:2023-05 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE 73rd Electronic Components and Technology Conference (ECTC)
language:
Short-container-title:

Author:

Molter Michael¹,Kumar Rahul²,Koller Sonja³,Bhatti Osama Waqar⁴,Ambasana Nikita⁵,Rosenbaum Elyse¹,Swaminathan Madhavan²

Affiliation:

1. University of Illinois Urbana-Champaign

2. Penn State University

3. Intel Deutschland GmbH

4. Georgia Institute of Technology

5. DPE, DCAI, Intel India

Funder

National Science Foundation

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10195193/10195244/10195639.pdf?arnumber=10195639

Reference22 articles.

1. A tutorial on Bayesian optimization of expensive cost functions, with application to active user modeling and hierarchical reinforcement learning;brochu;ArXiv,2010

2. A tutorial on Bayesian optimization;frazier;ArXiv,2018

3. Bayesian optimisation over multiple continuous and categorical inputs;ru;Proceedings of the 37th International Conference on Machine Learning,2020

4. Structure discovery in nonparametric regression through compositional kernel search;duvenaud;Proceedings of the 30th International Conference on Machine Learning,2013

5. Pymoo: Multi-Objective Optimization in Python

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Analysis and Design of the Interposer PDN With Optimal Arrangement of Decoupling Capacitors;IEEE Transactions on Components, Packaging and Manufacturing Technology;2024-02