A proposed DG-FinFET based SRAM cell design with RadHard capabilities-Reference-Cited by-同舟云学术

A proposed DG-FinFET based SRAM cell design with RadHard capabilities

Published:2010-08 Issue:8 Volume:50 Page:1181-1188
ISSN:0026-2714
Container-title:Microelectronics Reliability
language:en
Short-container-title:Microelectronics Reliability

Author:

Rathod S.S.,Saxena A.K.,Dasgupta S.

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference26 articles.

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3. Ioannou Dimitris P, Ioannou Dimitris E. Beta engineering and circuit styles for SEU hardening SOI SRAM cells. In: Proc international semiconductor device research symposium; December 2003. p. 262–3.

4. Logic synthesis of multilevel circuits with concurrent error detection;Touba;IEEE Trans Comput-aided Des,1997

5. Low power SEU immune CMOS memory circuits;Liu;IEEE Trans Nucl Sci,1992

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