Leakage Reduction in 18 nm FinFET based 7T SRAM Cell using Self Controllable Voltage Level Technique

Author:

Kumar T. Santosh,Tripathi Suman LataORCID

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering,Computer Science Applications

Cited by 19 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Design and Analysis of Si/GaSb HTFET-Based 7T SRAM Cell for Ultra-Low Voltage Applications;Silicon;2024-01-09

2. Design and simulation of low-power CMOS SRAM cells;Nanoscale Memristor Device and Circuits Design;2024

3. Designing power‐efficient SRAM cells with SGFinFETs using LECTOR technique;Software: Practice and Experience;2023-12-04

4. Design and Characterization of 6T SRAM bitcell using 18nm FinFET;2023 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER);2023-10-13

5. Design of high efficient low power static logic circuit using SG FinFET;International Journal of Electronics;2023-09-21

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