Logic operation‐based Design for Testability method and parallel test algorithm for 1T1R crossbar-Reference-Cited by-同舟云学术

Logic operation‐based Design for Testability method and parallel test algorithm for 1T1R crossbar

Published:2017-12 Issue:25 Volume:53 Page:1631-1632
ISSN:0013-5194
Container-title:Electronics Letters
language:en
Short-container-title:Electron. lett.

Author:

Liu Peng¹,You Zhiqiang¹,Kuang Jishun¹,Elimu Michael¹,Cai Shuo²,Wang Weizheng²

Affiliation:

1. Key Laboratory for Embedded and Network Computing of Hunan Province, College of Computer Science and Electronic EngineeringHunan UniversityChangsha410082People's Republic of China

2. College of Computer and Communication EngineeringChangsha University of Science and TechnologyHunan ShengPeople's Republic of China

Funder

National Natural Science Foundation of China

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/el.2017.2424

Reference6 articles.

1. Sneak-Path Testing of Crossbar-Based Nonvolatile Random Access Memories

2. Logic operation‐based DFT method and 1R memristive crossbar March‐like test algorithm;Liu P.;IEICE Electron. Express,2015

3. RRAM defect modeling and failure analysis based on March test and a novel squeeze‐search scheme;Chen C.Y.;Trans. Comput.,2015

4. Efficient March test algorithm for 1T1R cross‐bar with complete fault coverage

5. MAGIC—Memristor-Aided Logic

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