Hardware‐efficient slope‐error algorithm based PAM4 baud rate CDR scheme for 40 Gb/s receiver
Author:
Affiliation:
1. Institute of Microelectronics, Peking UniversityBeijing100871the People's Republic of China
Funder
National Natural Science Foundation of China
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/el.2018.1280
Reference5 articles.
1. Timing Recovery in Digital Synchronous Data Receivers
2. Half baud‐rate, low BER PAM‐4 CDR based on SS‐MMSE algorithm;Liu P.;Electron. Lett.,2016
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