Hybrid Timing Error Detector for Baud Rate Multilevel Clock and Data Recovery
Author:
Affiliation:
1. Department of Electrical and Computer Engineering, The Ohio State University, Columbus, OH, USA
Funder
Intel Circuits SRS
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
General Medicine
Link
http://xplorestaging.ieee.org/ielx7/8784029/10019301/10329284.pdf?arnumber=10329284
Reference18 articles.
1. Clock recovery in high-speed multilevel serial links
2. Hardware‐efficient slope‐error algorithm based PAM4 baud rate CDR scheme for 40 Gb/s receiver
3. Timing Recovery in Digital Synchronous Data Receivers
4. A 78mW 11.8Gb/s serial link transceiver with adaptive RX equalization and baud-rate CDR in 32nm CMOS
5. A 16Gb/s 3.7mW/Gb/s 8-tap DFE receiver and baud rate CDR with 30kppm tracking bandwidth
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