A 16Gb/s 3.7mW/Gb/s 8-tap DFE receiver and baud rate CDR with 30kppm tracking bandwidth
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx7/6679622/6690965/06690975.pdf?arnumber=6690975
Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Hybrid Timing Error Detector for Baud Rate Multilevel Clock and Data Recovery;IEEE Open Journal of Circuits and Systems;2023
2. Baud rate pattern-adaptable dual loop clock recovery for high speed serial links;2021 55th Asilomar Conference on Signals, Systems, and Computers;2021-10-31
3. A 12.5Gbps PI-based Quarter-Rate Clock and Data Recovery Circuit with an Adaptive filter of JESD204B Standard;2021 6th International Conference on Integrated Circuits and Microsystems (ICICM);2021-10-22
4. A 3x blind ADC-based CDR for a 20 dB loss channel;IEEE Transactions on Circuits and Systems I: Regular Papers;2015-06
5. A 16 Gb/s 3.7 mW/Gb/s 8-Tap DFE Receiver and Baud-Rate CDR With 31 kppm Tracking Bandwidth;IEEE Journal of Solid-State Circuits;2014-11
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