Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Cited by
321 articles.
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1. Clock‐and‐Data Recovery
PLL;Phase‐Locked Loops;2023-12-22
2. Hard-disk drive read-channel design trade-offs for areal densities beyond 2 Tb/in2;Analog Integrated Circuits and Signal Processing;2023-12-18
3. Real- Time Demonstration of All-Digital Clock Recovery for Satellite Communication;2023 Asia Communications and Photonics Conference/2023 International Photonics and Optoelectronics Meetings (ACP/POEM);2023-11-04
4. Baud-rate and IQ skew tolerant timing recovery scheme for short-reach coherent optical interconnet;2023 Asia Communications and Photonics Conference/2023 International Photonics and Optoelectronics Meetings (ACP/POEM);2023-11-04
5. A 32 Gb/s NRZ PI-Based Baud-Rate Digitial Clock and Data Recovery Circuit in 28nm CMOS Technology;2023 8th International Conference on Integrated Circuits and Microsystems (ICICM);2023-10-20