1. A Scalable Adaptive ADC/DSP-based 1.25-to-56Gbps/112Gbps High-Speed Transceiver Architecture Using Decision-Directed MMSE CDR in 16nm and 7nm;Xu,2021
2. A 460mW 112Gb/s DSP-Based Transceiver with 38dB Loss Compensation for Next-Generation Data Centers in 7nm FinFET Technology;Tamer,2020
3. A 56Gb/s 7.7mW/Gb/s PAM-4 Wireline Transceiver in 10nm FinFET Using MM-CDR-Based ADC Timing Skew Control and Low-Power DSP with Approximate Multiplier’;Byoung,2020
4. A 100Gb/s 1.1pJ/b PAM-4 RX with Dual-Mode 1-tap PAM4/3-tap NRZ Speculative DFE in 14nm CMOS FinFET;Alessandro,2019
5. A 1.41pJ/b 56Gb/s PAM-4 Wireline Receiver Employing Enhanced Pattern Utilization CDR and Genetic Adaptation Algorithms in 7nm CMOS;Shayan,2019