Design and Optimization of 22 nm Gate Length High-k/Metal gate NMOS Transistor
Author:
Publisher
IOP Publishing
Subject
General Physics and Astronomy
Link
http://stacks.iop.org/1742-6596/431/i=1/a=012026/pdf
Reference22 articles.
1. Advanced high-κ dielectric stacks with polySi and metal gates: Recent progress and current challenges
2. Roadmap for 22nm and beyond (Invited Paper)
3. Effective electron mobility in Si inversion layers in metal–oxide–semiconductor systems with a high-κ insulator: The role of remote phonon scattering
4. Optimizing CMOS technology for maximum performance
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1. Mathematical Modelling of Drain Current Enhancement in High-k FD MOSFET;2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS);2020-07
2. Minimum leakage current optimization on 22 nm SOI NMOS device with HfO2/WSix/Graphene gate structure using Taguchi method.;Journal of Physics: Conference Series;2020-03-01
3. Performance Analysis of n-Channel VDG-MOSFET with High Dielectric Permittivity;Lecture Notes in Mechanical Engineering;2019-07-04
4. Comparative Analysis of Process Parameter Variations in DGFinFET Device Using Statistical Methods;Journal of Physics: Conference Series;2018-11
5. Effects of High-k Dielectrics with Metal Gate for Electrical Characteristics of SOI TRI-GATE FinFET Transistor;Journal of Nano- and Electronic Physics;2016
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