Minimum leakage current optimization on 22 nm SOI NMOS device with HfO2/WSix/Graphene gate structure using Taguchi method.

Abstract

Abstract To acquire the optimal value of the performance parameter, a bilayer graphene with silicon on insulator (SOI) was enhanced and analyzed on 22 nm NMOS device. The device is made of Hafnium Dioxide (HfO2) as a high-k material whereas Tungsten Silicide (WSix) as a metal gate. The Silvaco software ATHENA and ATLAS modules were applied to simulate the fabrication process of virtual devices and to verify the device’s electrical properties accordingly. The Taguchi L9 orthogonal array method was then used to enhance the device process parameters minimum leakage current (ILEAK) according to the International Technology Roadmap Semiconductor (ITRS) specification of 100nA/μm maximum range. The result from smaller-the-better (STB) for ILEAK is then reviewed by the percentage affecting the process parameter. The simulation result shows that the halo tilting angle is the most dominant factor for ILEAK optimization process. The optimized results indicate excellent device performance with ILEAK = 9.29746 nA/µm which is far lower than the prediction.