Analytical modelling and design of 9T SRAM cell with leakage control technique
Author:
Publisher
Springer Science and Business Media LLC
Subject
Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing
Link
http://link.springer.com/content/pdf/10.1007/s10470-019-01483-1.pdf
Reference26 articles.
1. Maroof, N., & Kong, B. (2017). 10T SRAM using half-VDD precharge and row-wise dynamically powered read port for low switching power and ultralow RBL leakage. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25(4), 1193–1203.
2. Gupta, S., Gupta, K., & Pandey, N. (2017). A 32-nm Subthreshold 7T SRAM bit cell with read assist. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25(12), 3473–3483.
3. Oh, T. W., et al. (2017). Power-gated 9T SRAM cell for low-energy operation. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25(3), 1183–1187.
4. Senousy, R. E., Ibrahim, S., & Anis, W. (2016). Stability analysis and design methodology of near-threshold 6T SRAM cells. In 2016 28th International conference on microelectronics (ICM), Giza (pp. 225–228).
5. Arif, S., & Pal, S. (2015). Variation-resilient CNFET-based 8T SRAM cell for ultra-low-power application. In 2015 International conference on signal processing and communication engineering systems, Guntur (pp. 147–151).
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