10T SRAM Using Half- $V_{\text {DD}}$ Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage-Reference-Cited by-同舟云学术

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10T SRAM Using Half- $V_{\text {DD}}$ Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage

Published:2017-04 Issue:4 Volume:25 Page:1193-1203
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Maroof Naeem^ORCID,Kong Bai-Sun^ORCID

Funder

Basic Research Program through the National Research Foundation of Korea

Ministry of Education

Industrial Strategic Technology Development Program funded by the Ministry of Trade, Industry & Energy, Korea

IDEC, KAIST

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/7882729/07801981.pdf?arnumber=7801981

Cited by 34 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design of dual port 9T SRAM cell with parallel processing and high performance computing;Physica Scripta;2024-08-20

2. A Single Bitline Highly Stable, Low Power With High Speed Half-Select Disturb Free 11T SRAM Cell;ACM Transactions on Design Automation of Electronic Systems;2024-07-09

3. A Novel CNFET SRAM-Based Compute-In-Memory for BNN Considering Chirality and Nanotubes;Electronics;2024-06-04

4. A CNTFET based stable, single-ended 7T SRAM cell with improved write operation;Physica Scripta;2024-02-09

5. Design and simulation of low-power CMOS SRAM cells;Nanoscale Memristor Device and Circuits Design;2024

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