Performance evaluation of SRAM cell using FinFET-Reference-Cited by-同舟云学术

Performance evaluation of SRAM cell using FinFET

Published:2022-08-17 Issue: Volume: Page:
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Container-title:2022 3rd International Conference on Electronics and Sustainable Communication Systems (ICESC)
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Author:

P Dinesha.¹,Subba Reddy K.¹,Sai Vishal Reddy M.¹,Sri Harsha Phani S.¹,Chaitanya M.¹

Affiliation:

1. Dayananda Sagar College of Engineering Bangalore,Department of Electronics & Communication Engineering,Karnataka,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9885261/9885247/09885372.pdf?arnumber=9885372

Reference21 articles.

1. FinFET A Self Aligned Double-Gate MOSFET Scalable to 20nm;hisamoto;IEEE Transactions on Elecron Devices,2000

2. Improved Read Noise Margin Characteristics for Single Bit Line SRAM Cell Using Adiabatically Operated Word Lin;manna;IEEE International Conference on Nextgen Electronic Technologies,2017

3. A Novel Approach to Design SRAM Cells for Low Leakage and Improved Stability

4. Optimization of Power and Energy in FinFET Based SRAM Cell Using Adiabatic Logic;pati;IEEE International Conference on Nextgen Electronic Technologies,2017

5. Performance Analysis of SRAM at Different Technologies using Candence;padmanabha;International Journal of Electrical and Computer Engineering (IJECE),2020

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