A 32-nm Subthreshold 7T SRAM Bit Cell With Read Assist-Reference-Cited by-同舟云学术

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A 32-nm Subthreshold 7T SRAM Bit Cell With Read Assist

Published:2017-12 Issue:12 Volume:25 Page:3473-3483
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Gupta Shourya^ORCID,Gupta Kirti,Pandey Neeta

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/8118264/08030353.pdf?arnumber=8030353

Cited by 43 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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2. Design of Radiation Hardened SRAM Cell with High Speed and Write Stability for Space Applications;2024 IEEE International Conference on Information Technology, Electronics and Intelligent Communication Systems (ICITEICS);2024-06-28

3. Silicon cross-coupled gated tunneling diodes;Chip;2024-06

4. Design of low power SRAM cells with increased read and write performance using Read - Write assist technique;e-Prime - Advances in Electrical Engineering, Electronics and Energy;2024-03

5. Design and Comparison of SEU Tolerant 10T Memory Cell for Radiation Environment Applications;EAI Endorsed Transactions on Energy Web;2024-02-01

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