Exploiting Reconfigurability for Effective Testing of Delay Faults in Sequential Subcircuits of LUT-based FPGAs
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Publisher
Springer Berlin Heidelberg
Link
http://link.springer.com/content/pdf/10.1007/3-540-46117-5_64
Reference14 articles.
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1. Optimization of Testability of Sequential Circuits Implemented in FPGAs with Embedded Memory;Field Programmable Logic and Application;2004
2. On Determining the Speed of Circuits Implemented With LUT-Based FPGA'S;IFAC Proceedings Volumes;2003-02
3. Evaluation of Testability of Path Delay Faults for User-Configured Programmable Devices;Field Programmable Logic and Application;2003
4. Exploiting Reconfigurability for Effective Testing of Delay Faults in Sequential Subcircuits of LUT-based FPGAs;Lecture Notes in Computer Science;2002
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