On Determining the Speed of Circuits Implemented With LUT-Based FPGA'S-Reference-Cited by-同舟云学术

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On Determining the Speed of Circuits Implemented With LUT-Based FPGA'S

Published:2003-02 Issue:1 Volume:36 Page:195-200
ISSN:1474-6670
Container-title:IFAC Proceedings Volumes
language:en
Short-container-title:IFAC Proceedings Volumes

Author:

Krasniewski Andrzej

Publisher

Elsevier BV

Subject

General Medicine

Reference13 articles.

1. Certified Timing Verification and the Transition Delay of a Logic Circuit;Devadas;Proc. 29th Design Automation Conf.,1992

2. RESIST: A Recursive Test Pattern Generation Algorithm for Path Delay Faults Considering Various Test Classes;Fuchs;IEEE Trans. on CAD,1994

3. BIST-Based Delay Path Testing in FPGA Architectures;Harris;Proc. IEEE Int. Test Conf.,2001

4. Application-Dependent Testing of FPGA Delay Faults;Krasniewski;Proc. 25th EUROMICRO Conf.,1999

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