BIST-based delay path testing in FPGA architectures-Reference-Cited by-同舟云学术

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BIST-based delay path testing in FPGA architectures

Published: Issue: Volume: Page:
ISSN:
Container-title:Proceedings International Test Conference 2001 (Cat. No.01CH37260)
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Author:

Harris I.G.,Menon P.R.,Tessier R.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/7640/20866/00966717.pdf?arnumber=966717

Cited by 32 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Path Delay Measurement with Correction for Temperature And Voltage Variations;2020 IEEE International Test Conference in Asia (ITC-Asia);2020-09

2. On-Chip Delay Measurement for Degradation Detection And Its Evaluation under Accelerated Life Test;2020 IEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS);2020-07

3. On-Chip Delay Measurement for In-Field Test of FPGAs;2019 IEEE 24th Pacific Rim International Symposium on Dependable Computing (PRDC);2019-12

4. On-Chip Test Clock Validation Using A Time-to-Digital Converter in FPGAs;2019 IEEE International Test Conference in Asia (ITC-Asia);2019-09

5. Worst Case Test Vectors for Sequential Circuits in Flash-Based FPGAs Exposed to Total Dose;IEEE Transactions on Nuclear Science;2019-07

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