Evaluation of Testability of Path Delay Faults for User-Configured Programmable Devices

Author:

Krasniewski Andrzej

Publisher

Springer Berlin Heidelberg

Reference16 articles.

1. Krstic, A., Liou, J.-J.: Delay Testing Considering Crosstalk-Induced Effects. In: Proc. IEEE Int. Test Conf., pp. 558-567 (2001)

2. Metra, C., Pagano, A., Ricco, B.: On-Line Testing of Transient and Crosstalk Faults Affecting Interconnections of FPGA-Implemented Systems. In: Proc. IEEE Int. Test Conf., pp. 939-947 (2001)

3. Abramovici, M., Stroud, C.: BIST-Based Delay-Fault Testing in FPGAs. In: Proc. IEEE Int. On-Line Testing Workshop (2002)

4. Renovell, M., Faure, P., Portal, J.M., Figueras, J., Zorian, Y.: IS-FPGA: A New Symmetric FPGA Architecture with Implicit SCAN. In: Proc. IEEE Int. Test Conf., pp. 924-931 (2001)

5. Krasniewski, A.: Application-Dependent Testing of FPGA Delay Faults. In: Proc. 25th EUROMICRO Conf., vol. 1, pp. 260-267 (1999)

Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations;ACM Transactions on Reconfigurable Technology and Systems;2008-06

2. Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations;ACM Transactions on Reconfigurable Technology and Systems;2008-03

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