Impact of channel length, gate insulator thickness, gate insulator material, and temperature on the performance of nanoscale FETs-Reference-Cited by-同舟云学术

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Impact of channel length, gate insulator thickness, gate insulator material, and temperature on the performance of nanoscale FETs

Published:2018-09-05 Issue:4 Volume:17 Page:1521-1527
ISSN:1569-8025
Container-title:Journal of Computational Electronics
language:en
Short-container-title:J Comput Electron

Author:

Saha Jibesh K.^ORCID,Chakma Nitish,Hasan Mehedhi^ORCID

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering,Modeling and Simulation,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Link

http://link.springer.com/article/10.1007/s10825-018-1235-4/fulltext.html

Reference28 articles.

1. Kranti, A., Armstrong, G.A.: Optimization of the source/drain extension region profile for suppression of short channel effects in sub-50 nm DG MOSFETs with high-κ gate dielectrics. Semicond. Sci. Technol. 21(12), 1563–1572 (2006)

2. Antoniadis, D.A., Aberg, I., Chléirigh, C.N., et al.: Continuous MOSFET performance increase with device scaling: the role of strain and channel material innovations. IBM J. Res. Dev. 50(4/5), 363–376 (2006)

3. Khanna, V.K.: Integrated Nanoelectronics: Nanoscale CMOS, Post-CMOS and Allied Nanotechnologies, Nanoscience and Technology, pp. 45–100. Springer, New Delhi (2016)

4. Liu, H., Neal, A.T., Ye, P.D.: Channel length scaling of MoS2 MOSFETs. ACS Nano 6(10), 8563–8569 (2012)

5. Robertson, J.: High dielectric constant gate oxides for metal oxide Si transistors. Rep. Prog. Phys. 69(2), 327 (2005)

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