Impact of Scaling on Nanosheet FET and CMOS Circuit Applications

Abstract

In this paper, the impact of scaling on the gate all around the nanosheet field effect transistor (GAA NSFET) is assessed in detail at sub-5-nm nodes for digital and analog/RF applications. The gate length (LG) is downscaled from 20 nm to 5 nm to analyse the various DC and analog/RF performance metrics by fixing the remaining device design parameters. When LG is downscaled from 20 nm to 5 nm, I ON is improved by 2.1×, I OFF increases by three orders in magnitude, SS increases by 27%, DIBL is increased by 4×, and a Vth roll off of 41 mV is noticed. Further, an enhancement of 3.65× was noticed in cut-off frequency (f T) with downscaling of LG from 20 nm to 5 nm. On top of that, the circuit level performance is analysed with LG scaling. The lookup table based Verilog-A model is used in the Cadence Virtuoso tool to demonstrate the circuit performance. The CMOS inverter and ring oscillator’s performance was studied in detail with LG scaling. With LG scaling from 20 nm to 5 nm, the inverter performance metrics like switching current (I SC) is increased by 3.87×, propagation delay (τP), energy delay product (EDP) and power delay product (PDP) are reduced by 65%, 5.5× and 1.95× respectively. Moreover, the ring oscillator offers superior performance with an oscillation frequency (f OSC) of 98.05 GHz when LG is scaled to 5 nm, which is 157% more than f OSC at LG of 20 nm. Thus, with downscaling DC performance degraded due to the SCEs. However, the RF performance of the device improved with downscaling of LG towards lower nodes. Thus, the analyses reveal the scaling capability of NSFET at both device and circuit levels for sub-5-nm nodes.