The Coupling Model for Function and Delay Faults
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering
Link
http://link.springer.com/content/pdf/10.1007/s10836-005-3476-y.pdf
Reference25 articles.
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3. M.J. Batek and J.P. Hayes, “Test-Set Preserving Logic Transformations,” in Proc. Design Automation Conf., pp. 454–458, 1992.
4. R. Betancourt, “Derivation of Minimum Test Sets for Unate Logic Circuits,” IEEE Trans. on Computers, vol. C-20, no. 11, pp. 1264–1269, 1971.
5. K.-T. Cheng, A. Krstic, and H-C Chen, “Generation of High Quality Tests for Robustly Untestable Path Delay Faults,” IEEE Trans. on Computers, vol. 45, no. 12, pp. 1379–1392, 1996.
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