Test generation at the algorithm-level for gate-level fault coverage-Reference-Cited by-同舟云学术

Test generation at the algorithm-level for gate-level fault coverage

Published:2008-07 Issue:7 Volume:48 Page:1093-1101
ISSN:0026-2714
Container-title:Microelectronics Reliability
language:en
Short-container-title:Microelectronics Reliability

Author:

Bareisa Eduardas,Jusas Vacius,Motiejunas Kestutis,Seinauskas Rimantas

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference18 articles.

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2. Chiusano S, Corno F, Prinetto P. A test pattern generation algorithm exploiting behavioral information. In: Proceedings of seventh Asian test symposium (ATS’98), Singapore, December 1998. p. 480–85.

3. Rudnick EM, Vietti R, Ellis A, Corno F, Prinetto P, Sonza Reorda M. Fast sequential circuit test generation using high-level and gate-level techniques. In: Proceedings of IEEE design, automation and test in Europe, February 1998. p. 570–76.

4. Test generation and testability alternatives exploration of critical algorithms for embedded applications;Ferrandi;IEEE Trans Comput,2002

5. Cho CH, and Armstrong JR. B-algorithm: a behavioral test generation algorithm. In: Proceedings of international test conference, October 1994. p. 968–79.

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