1. Underwood B, Law WO, Kang S, Konuk H. Fastpath: a path-delay test generator for standard scan designs. In: Proceedings of 1994 international test conference (1994); 1994. p. 154–63.
2. Pomeranz I, Reddy SM. On testing delay faults in macro-based combinational circuits. In: Proceedings of international conference on computer-aided-design, San Jose, CA; 1994. p. 332–9.
3. Pomeranz I, Reddy SM. Functional test generation for delay faults in combinational circuits. In: Proceedings of 1995 international conference on computer-aided-design (1995); 1995. p. 687–94.
4. Realization-independent ATPG for designs with unimplemented blocks;Kim;IEEE Trans CAD,2001
5. Yi J, Hayes JP. a fault model for function and delay testing. In: Proceedings of the IEEE European test workshop, ETW’ 01; 2001. p. 27–34.