Path delay test generation at functional level-Reference-Cited by-同舟云学术

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Path delay test generation at functional level

Published:2015-05 Issue:3 Volume:9 Page:135-141
ISSN:1751-8601
Container-title:IET Computers & Digital Techniques
language:en
Short-container-title:IET Computers & Digital Techniques

Author:

Bareisa Eduardas¹,Jusas Vacius¹,Motiejunas Kestutis¹,Seinauskas Rimantas¹

Affiliation:

1. Software Engineering DepartmentKaunas University of TechnologyStudentų 50‐404LT‐51368KaunasLithuania

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cdt.2013.0096

Reference21 articles.

1. Ahmed N. Tehranipoor M. Jayaram V.: ‘Timing‐based delay test for screening small delay defects’.Proc. of Design Automation Conf. 2006 paper 19.2

2. High‐quality transition fault ATPG for small delay defects;Kumar M.;IEEE Trans. Comput.‐Aided Des. Integr. Circuits Syst.,2007

3. Efficient Path Delay Test Generation for Custom Designs

4. Functional delay test generation based on software prototype;Bareisa E.;Microelectron. Reliab.,2009

5. Sharma M. Patel J.H.: ‘Finding a small set of longest testable paths that cover every gate’.Proc. Int. Test Conf. Baltimore MD October2002 pp.974–982

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1. Formal verification methodology for real‐time Field Programmable Gate Array;IET Computers & Digital Techniques;2017-08-09

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