Formal verification methodology for real‐time Field Programmable Gate Array
Author:
Affiliation:
1. Department of Electrical and Computer EngineeringNorth Dakota State University1411 Centennial BlvdND 58102FargoUSA
2. Department of Electrical EngineeringCOMSATS Institute of Information TechnologyPark RoadChak ShahzadIslamabadPakistan
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cdt.2016.0189
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