Functional fault models for non-scan sequential circuits-Reference-Cited by-同舟云学术

Functional fault models for non-scan sequential circuits

Published:2011-12 Issue:12 Volume:51 Page:2402-2411
ISSN:0026-2714
Container-title:Microelectronics Reliability
language:en
Short-container-title:Microelectronics Reliability

Author:

Bareisa Eduardas,Jusas Vacius,Motiejunas Kestutis,Seinauskas Rimantas

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference19 articles.

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2. Chen G, Reddy SM, Pomeranz I. Procedures for identifying untestable and redundant transition faults in synchronous sequential circuits. In: Proceedings of the 21st international conference on computer design (ICCD’03); 2003. p. 36–41.

3. Majumder S, Agrawal VD, Bushnell ML. Path delay testing: variable-clock versus rated-clock. In: Proceedings of the 11th international conference on VLSI design; January 1998. p. 470–5.

4. Bose S, Agrawal VD. Sequential logic path delay test generation by symbolic analysis. In: Proceedings of the 4th Asian test symposium; November 1995. p. 353–9.

5. Barzilai Z, Rosen B. Comparison of AC self-testing procedures. In: Proceedings of the IEEE international test conference; 1983. p. 89–94.

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