Universal Test Sets for Logic Networks-Reference-Cited by-同舟云学术

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Universal Test Sets for Logic Networks

Published:1973-09 Issue:9 Volume:C-22 Page:835-839
ISSN:0018-9340
Container-title:IEEE Transactions on Computers
language:
Short-container-title:IEEE Trans. Comput.

Author:

Akers Sheldon B.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Theoretical Computer Science,Software

Link

http://xplorestaging.ieee.org/ielx5/12/5009165/05009174.pdf?arnumber=5009174

Cited by 27 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Efficient testing of multi‐output combinational cells in nano‐complementary metal oxide semiconductor integrated circuits;IET Computers & Digital Techniques;2014-03

2. Robust Coupling Delay Test Sets;Journal of Electronic Testing;2012-04-13

3. Implementing Symmetric Functions with Hierarchical Modules for Stuck-At and Path-Delay Fault Testability;Journal of Electronic Testing;2006-04

4. High-level delay test generation for modular circuits;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2006-03

5. The Coupling Model for Function and Delay Faults;Journal of Electronic Testing;2005-12

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