High-level delay test generation for modular circuits-Reference-Cited by-同舟云学术

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High-level delay test generation for modular circuits

Published:2006-03 Issue:3 Volume:25 Page:576-590
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Joonhwan Yi ,Hayes J.P.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx5/43/33596/01597390.pdf?arnumber=1597390

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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2. Diagnostic Modeling of Digital Systems with Multi-Level Decision Diagrams;Geographic Information Systems;2013

3. Robust Coupling Delay Test Sets;Journal of Electronic Testing;2012-04-13

4. A SAT Based Test Generation Method for Delay Fault Testing of Macro Based Circuits;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2011-04

5. Functional delay test generation based on software prototype;Microelectronics Reliability;2009-12

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