Process-Variation and Temperature Aware SoC Test Scheduling Technique
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering
Link
http://link.springer.com/content/pdf/10.1007/s10836-013-5374-z.pdf
Reference28 articles.
1. Aghaee N, Peng Z, Eles P (2011) Adaptive temperature-aware SoC test scheduling considering process variation. Digit syst des, pp 197–204
2. Aghaee N, Peng Z, Eles P (2011) Process-variation and temperature aware soc test scheduling using particle swarm optimization. Int des and test, pp 1–6
3. Aghaee N, He Z, Peng Z, Eles P (2010) Temperature-aware SoC test scheduling considering inter-chip process variation. Asian test symposium, pp 395–398
4. Bonhomme Y, Girard P, Landrault C, Pravossoudovitch S (2002) Test power: a big issue in large SOC designs. Electron des, test, and appl, pp 447–449
5. Chandran U, Zhao D (2009) Thermal driven test access routing in hyper-interconnected three-dimensional System-on-Chip. Defect and fault toler in VLSI syst, pp 410–418
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1. Genetic Algorithm-based thermal uniformity–aware X-filling to reduce peak temperature during testing;Measurement and Control;2018-07-02
2. Thermal-aware SoC Test Scheduling with Voltage/Frequency Scaling and Test Partition;Journal of Electronic Testing;2018-06-06
3. Thermal Aware Test Scheduling for NTV Circuit;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2018-04
4. Temperature-Gradient-Based Burn-In and Test Scheduling for 3-D Stacked ICs;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2015-12
5. A Test-Ordering Based Temperature-Cycling Acceleration Technique for 3D Stacked ICs;Journal of Electronic Testing;2015-11-16
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