Thermal-aware SoC Test Scheduling with Voltage/Frequency Scaling and Test Partition-Reference-Cited by-同舟云学术

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Thermal-aware SoC Test Scheduling with Voltage/Frequency Scaling and Test Partition

Published:2018-06-06 Issue:4 Volume:34 Page:447-460
ISSN:0923-8174
Container-title:Journal of Electronic Testing
language:en
Short-container-title:J Electron Test

Author:

Zhang Ying,Ling Li,Jiang Jianhui,Xiao Jie

Funder

National Natural Science Foundation of China

Zhejiang Provincial Natural Science Foundation of China

Fundamental Research Funds for the Central Universities

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering

Link

http://link.springer.com/article/10.1007/s10836-018-5733-x/fulltext.html

Reference32 articles.

1. Aghaee N, Peng Z, Eles P (2013) Process-variation and temperature aware SoC test scheduling technique. J Electron Test 29(4):499–520

2. Aghaee N, Peng Z, Eles P (2015) A test-ordering based temperature-cycling acceleration technique for 3D stacked ICs. J Electron Test 31(5-6):503–523

3. Bild DR, Misra S, Chantemy T, Kumar P, Dick RP, Huy XS, Shangz L, Choudhary A (2008) Temperature-aware test scheduling for multiprocessor systems-on-chip. In: Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, San Jose, USA, pp 59–66

4. Chakrabarty K (2000) Test scheduling for core-based systems using mixed-integer linear programming. IEEE Trans Comput-Aid Des Integr Circuit Syst 19(10):1163–1174

5. Chakrabarty K (2005) Low-cost modular testing and test resource partitioning for SOCs. In: Proceedings of IEEE Computers and Digital Techniques, vol 152, pp 427–441

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