A Test-Ordering Based Temperature-Cycling Acceleration Technique for 3D Stacked ICs
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering
Link
http://link.springer.com/content/pdf/10.1007/s10836-015-5541-5.pdf
Reference39 articles.
1. Aghaee N, Peng Z, Eles P (2013) Temperature-gradient based test scheduling for 3D stacked ICs. Proc. 20th IEEE Int. Conf. Electron. Circuits Syst. pp 405–408
2. Aghaee N, Peng Z, Eles P (2013) Process-variation and temperature aware SoC test scheduling technique. J Electron Test Theory Applic. 29:499–520
3. Aghaee N, Peng Z, Eles P (2014) An efficient temperature-gradient based burn-in technique for 3D stacked ICs. Proc. Des. Autom. Test Eur.
4. Aghaee N, Peng Z, Eles P (2015) Temperature-gradient-based burn-in and test scheduling for 3-D Stacked ICs. IEEE Trans Very Large Scale Integr VLSI Syst
5. Aghaee N, Peng Z, Eles P (2015) An integrated temperature-cycling acceleration and test technique for 3D stacked ICs. Proc. 20th Asia S. Pac. Des. Autom. Conf. pp 526–531
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1. Thermal-aware SoC Test Scheduling with Voltage/Frequency Scaling and Test Partition;Journal of Electronic Testing;2018-06-06
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