Thermal Driven Test Access Routing in Hyper-interconnected Three-Dimensional System-on-Chip-Reference-Cited by-同舟云学术

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Thermal Driven Test Access Routing in Hyper-interconnected Three-Dimensional System-on-Chip

Published:2009-10 Issue: Volume: Page:
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Container-title:2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
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Author:

Chandran Unni,Zhao Dan

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/5372211/5372212/05372230.pdf?arnumber=5372230

Cited by 10 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Frequency-scaled thermal-aware test scheduling for 3D ICs using machine learning based temperature estimation;Microelectronics Journal;2022-10

2. Power-aware partitioning and test time reduction for 3D-SoC;Innovations in Systems and Software Engineering;2022-09-06

3. Machine Learning based Temperature Estimation for Test Scheduling of 3D ICs;2020 IEEE International Test Conference India;2020-07

4. Test-Time Reduction for Power-Aware 3D-SoC;2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID);2018-01

5. Dual-Speed TAM Optimization of 3D SoCs for Mid-bond and Post-bond Testing;2014 IEEE 23rd Asian Test Symposium;2014-11

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