Temperature-Gradient-Based Burn-In and Test Scheduling for 3-D Stacked ICs-Reference-Cited by-同舟云学术

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Temperature-Gradient-Based Burn-In and Test Scheduling for 3-D Stacked ICs

Published:2015-12 Issue:12 Volume:23 Page:2992-3005
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Aghaee Nima^ORCID,Peng Zebo,Eles Petru

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/7333028/07004891.pdf?arnumber=7004891

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Automating the Generation of Programs Maximizing the Repeatable Constant Switching Activity in Microprocessor Units via MaxSAT;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-11

2. Scalable Multi-Stage CMOS OTAs With a Wide C_L-Drivability Range Using Low-Frequency Zeros;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-01

3. A Hybrid Metaheuristic for the Unrelated Parallel Machine Scheduling Problem;Mathematics;2021-04-01

4. Thermal Aware Test Scheduling for NTV Circuit;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2018-04

5. A Test-Ordering Based Temperature-Cycling Acceleration Technique for 3D Stacked ICs;Journal of Electronic Testing;2015-11-16

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