Automating the Generation of Programs Maximizing the Repeatable Constant Switching Activity in Microprocessor Units via MaxSAT
Author:
Affiliation:
1. Department of Control and Computer Engineering, Politecnico di Torino, Turin, Italy
2. Institute of Computer Science, University of Freiburg, Freiburg im Breisgau, Germany
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software
Link
http://xplorestaging.ieee.org/ielx7/43/10288105/10058568.pdf?arnumber=10058568
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1. Instruction-based self-test for delay faults maximizing operating temperature
2. PHAETON: A SAT-Based Framework for Timing-Aware Path Sensitization
3. Temperature-Aware Software-Based Self-Testing for Delay Faults
4. Towards SAT-Based SBST Generation for RISC-V Cores
5. System-Level Test: State of the Art and Challenges
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1. Branch-Aware Self-Test Program Generation for Processor Cores;2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA);2024-04-22
2. A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors;2023 IEEE European Test Symposium (ETS);2023-05-22
3. Functional Testing with STLs: A Step Towards Reliable RISC-V-based HPC Commodity Clusters;Lecture Notes in Computer Science;2023
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