A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors-Reference-Cited by-同舟云学术

A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors

Published:2023-05-22 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE European Test Symposium (ETS)
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Author:

Anders Jens¹,Andreu Pablo²,Becker Bernd³,Becker Steffen⁴,Cantoro Riccardo⁵,Deligiannis Nikolaos I.⁵,Elhamawy Nourhan⁶,Faller Tobias³,Hernandez Carles²,Mentens Nele⁷,Rizi Mahnaz Namazi⁷,Polian Ilia⁶,Sajadi Abolfazl⁷,Sauer Mathias⁸,Schwachhofer Denis⁶,Reorda Matteo Sonza⁵,Stefanov Todor⁷,Tuzov Ilya²,Wagner Stefan⁴,Zidarič Nuša⁷

Affiliation:

1. University of Stuttgart,Institute of Smart Sensors,Stuttgart,Germany

2. Universitat Politècnica de València,Spain

3. University of Freiburg,Dpt. of Computer Science,Freiburg,Germany

4. University of Stuttgart,Institute of Software Engineering,Stuttgart,Germany

5. Politecnico di Torino,Dpt. of Control and Computer Engineering,Turin,Italy

6. University of Stuttgart,Institute of Computer Architecture and Computer Engineering,Stuttgart,Germany

7. Leiden University,LIACS,Leiden,Netherlands

8. Advantest Europe,Boeblingen,Germany

Funder

Ministry of Education

Agencia Estatal de Investigación

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10173930/10173940/10174099.pdf?arnumber=10174099

Reference86 articles.

1. Low-power high-performance 32-bit RISC-V microcontroller on 65-nm silicon-on-thin-BOX (SOTB)

2. Hybrid Modular Redundancy: Exploring Modular Redundancy Approaches in RISC-V Multi-Core Computing Clusters for Reliable Processing in Space;rogenmoser,2023

3. Technology mediated tutorial on RISC-V CPU core implementation and sign-off using revolutionary EDA management system (EMS) — VSDFLOW

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3. Towards Dependable RISC-V Cores for Edge Computing Devices;2023 IEEE 29th International Symposium on On-Line Testing and Robust System Design (IOLTS);2023-07-03