Low-power high-performance 32-bit RISC-V microcontroller on 65-nm silicon-on-thin-BOX (SOTB)-Reference-Cited by-同舟云学术

Low-power high-performance 32-bit RISC-V microcontroller on 65-nm silicon-on-thin-BOX (SOTB)

Published:2020-10-25 Issue:20 Volume:17 Page:20200282-20200282
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Hoang Trong-Thuc¹²,Duran Ckristian¹,Nguyen Khai-Duy¹³,Dang Tuan-Kiet¹³,Nhu Quynh Nguyen Quang³,Than Phuc Hong⁴,Tran Xuan-Tu⁵,Le Duc-Hung⁶,Tsukamoto Akira²,Suzaki Kuniyasu²⁷,Pham Cong-Kha¹

Affiliation:

1. University of Electro-Communications (UEC)

2. National Institution of Advanced Industrial Science and Technology (AIST)

3. The University of Danang, University of Science and Technology (DUT)

4. Duy Tan University (DTU)

5. University of Engineering and Technology (VNU-UET)

6. University of Science (VNU-HCMUS)

7. Technology Research Association of Secure IoT Edge application based on RISC-V Open architecture (TRASIO)

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/elex/17/20/17_17.20200282/_pdf

Reference30 articles.

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2. [2] Wikipedia: ARM architecture (2020) https://en.wikipedia.org/wiki/ARM_architecture.

3. [3] Wikipedia: Reduced instruction set computer (2020) https://en.wikipedia.org/wiki/Reduced_instruction_set_computer.

4. [4] R. Goodwins: Chips that pass in the night: How risky is RISC-V to Arm, Intel and the others? Very (2020) https://www.theregister.co.uk/2020/03/09/risc_v_intel_amd_arm/.

5. [5] A. Waterman, et al.: The RISC-V instruction set manual, vol. I, ver. 2.0, UCB/EECS-2014-54, EECS Department, University of California, Berkeley (2014) https://www2.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-54.pdf.

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