A design approach of bonding head guiding platform for die to wafer hybrid bonding application using compliant mechanism

Author:

Nguyen Duc Nam,Dang Minh Phung,Dixit Saurav,Dao Thanh-PhongORCID

Funder

Industrial University of Ho Chi Minh City

Publisher

Springer Science and Business Media LLC

Subject

Industrial and Manufacturing Engineering,Modeling and Simulation

Reference17 articles.

1. Gao, G., Workman, T., Uzoh, C., Bang, K.M., Mirkarimi, L., Theil, J., Suwito, D., Katkar, R., Fountain, G., Guevara, G., Lee, B.: Die to wafer stacking with low temperature hybrid bonding. In: Proceedings of the Electronic Components and Technology Conference 2020 June, 589–594 (2020). https://doi.org/10.1109/ECTC32862.2020.00098

2. Bourjot, E., Stewart, P., Dubarry, C., Lagoutte, E., Rolland, E., Bresson, N., Romano, G., Scevola, D., Balan, V., Dechamp, J., Zussy, M., Mauguen, G., Castan, C., Sanchez, L., Jouve, A., Fournel, F., Cheramy, S.: Towards a complete direct hybrid bonding D2W integration flow: known-good-dies and die planarization modules development. In: 2019 International 3D Systems Integration Conference (2019). https://doi.org/10.1109/3DIC48104.2019.9058783

3. Sanchez, L., Bally, L., Montmayeul, B., Fournel, F., Dafonseca, J., Augendre, E., Di Cioccio, L., Carron, V., Signamarcheix, T., Taibi, R., Mermoz, S., Lecarpentier, G.: Chip to wafer direct bonding technologies for high density 3D integration. In: Proceedings of the Electronic Components and Technology Conference, 1960–1964 (2012). https://doi.org/10.1109/ECTC.2012.6249108

4. Katti, G., Mercha, A., Van Olmen, J., Huyghebaert, C., Jourdain, A., Stucchi, M., Rakowski, M., Debusschere, I., Soussan, P., Dehaene, W., De Meyer, K., Travaly, Y., Beyne, E., Biesemans, S., Swinnen, B.: 3D stacked ICs using Cu TSVs and die to wafer hybrid collective bonding. In: 2009 IEEE International Electron Devices Meeting (IEDM), 357–360 (2009). https://doi.org/10.1109/IEDM.2009.5424351

5. Gao, G., Mirkarimi, L., Workman, T., Guevara, G., Theil, J., Uzoh, C., Fountain, G., Lee, B., Mrozek, P., Huynh, M., Katkar, R.: Development of low temperature direct bond interconnect technology for die-to-wafer and die-to-die applications-stacking, yield improvement, reliability assessment. In: 2018 International Wafer Level Packaging Conference (IWLPC), 2018, 1–7 (2018). https://doi.org/10.23919/IWLPC.2018.8573278

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