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An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC

  • Published:2012-11 Issue:11 Volume:47 Page:2763-2772
  • ISSN:0018-9200
  • Container-title:IEEE Journal of Solid-State Circuits
  • language:
  • Short-container-title:IEEE J. Solid-State Circuits

Author:

Hegong Wei ,Chi-Hang Chan ,U-Fat Chio ,Sai-Weng Sin ,Seng-Pan U ,Martins R. P.,Maloberti F.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 56 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 10b 700 MS/s Single-Channel 1b/Cycle SAR ADC Using a Monotonic-Specific Feedback SAR Logic With Power-Delay-Optimized Unbalanced N/P-MOS Sizing;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-12

2. A 7-bit 3.8-GS/s 2-Way Time-Interleaved 4-bit/Cycle SAR ADC 16× Time-Domain Interpolation in 28-nm CMOS;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-09

3. A Column-Parallel Time-Interleaved SAR/SS ADC for Computing in Memory with 2-8bit Reconfigurable Resolution;2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS);2023-06-11

4. An Energy-Efficient SAR ADC With a Coarse-Fine Bypass Window Technique;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-01

5. An energy efficient symmetrical DAC switching scheme for single-ended SAR ADCs with zero reset energy and a 3-stage common-mode insensitive regenerative comparator;AEU - International Journal of Electronics and Communications;2022-12
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