An energy efficient symmetrical DAC switching scheme for single-ended SAR ADCs with zero reset energy and a 3-stage common-mode insensitive regenerative comparator-Reference-Cited by-同舟云学术

An energy efficient symmetrical DAC switching scheme for single-ended SAR ADCs with zero reset energy and a 3-stage common-mode insensitive regenerative comparator

Published:2022-12 Issue: Volume:157 Page:154421
ISSN:1434-8411
Container-title:AEU - International Journal of Electronics and Communications
language:en
Short-container-title:AEU - International Journal of Electronics and Communications

Author:

Pahlavanzadeh Hadi^ORCID,Karami Mohammad Azim

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering

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4. A 10 bit 5 MS/s column SAR ADC with digital error correction for CMOS image sensors;Xie;IEEE Trans Circ Syst II Exp Briefs,2019

5. 2.45 e-RMS Low-Random-Noise, 598.5 mW Low-Power, and 1.2 kfps High-Speed 2-Mp Global Shutter CMOS Image Sensor With Pixel-Level ADC and Memory;Seo;IEEE J Solid-State Circ,2022

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