2.45 e-RMS Low-Random-Noise, 598.5 mW Low-Power, and 1.2 kfps High-Speed 2-Mp Global Shutter CMOS Image Sensor With Pixel-Level ADC and Memory-Reference-Cited by-同舟云学术

2.45 e-RMS Low-Random-Noise, 598.5 mW Low-Power, and 1.2 kfps High-Speed 2-Mp Global Shutter CMOS Image Sensor With Pixel-Level ADC and Memory

Published:2022-04 Issue:4 Volume:57 Page:1125-1137
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Seo Min-Woong¹^ORCID,Chu Myunglae¹^ORCID,Jung Hyun-Yong¹^ORCID,Kim Suksan¹,Song Jiyoun¹,Bae Daehee¹^ORCID,Lee Sanggwon¹,Lee Junan²^ORCID,Kim Sung-Yong²,Lee Jongyeon²,Kim Minkyung¹,Lee Gwi-Deok¹^ORCID,Shim Heesung¹,Um Changyong¹,Kim Changhwa¹,Baek In-Gyu¹,Kwon Doowon¹,Kim Hongki¹,Choi Hyuksoon¹,Go Jonghyun¹,Ahn Jungchak²,Lee Jae-Kyu¹,Moon Chang-Rok¹,Lee Kyupil³,Kim Hyoung-Sub¹

Affiliation:

1. Semiconductor Research and Development Center, Samsung Electronics, Hwaseong-si, South Korea

2. System LSI, Samsung Electronics, Hwaseong-si, South Korea

3. Samsung Institute of Technology (SSIT), Samsung Electronics, Yongin-si, South Korea

Funder

Samsung Electronics’ Internal Research Fund

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/9741814/09701661.pdf?arnumber=9701661

Reference32 articles.

1. 8.3 M-Pixel 480-fps Global-Shutter CMOS Image Sensor with Gain-Adaptive Column ADCs and Chip-on-Chip Stacked Integration

2. 4.6 A 1/2.3inch 20Mpixel 3-layer stacked CMOS Image Sensor with DRAM

3. Noise Analysis for Comparator-Based Circuits

4. A back-illuminated global-shutter CMOS image sensor with pixel-parallel 14b subthreshold ADC

5. A Stacked CMOS Image Sensor With Array-Parallel ADC Architecture

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