A 10b 700 MS/s Single-Channel 1b/Cycle SAR ADC Using a Monotonic-Specific Feedback SAR Logic With Power-Delay-Optimized Unbalanced N/P-MOS Sizing-Reference-Cited by-同舟云学术

A 10b 700 MS/s Single-Channel 1b/Cycle SAR ADC Using a Monotonic-Specific Feedback SAR Logic With Power-Delay-Optimized Unbalanced N/P-MOS Sizing

Published:2023-12 Issue:12 Volume:70 Page:4767-4780
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Guo Mingqiang¹^ORCID,Qi Liang²^ORCID,Zhao Weibing³,Xiao Gangjun³,Martins Rui P.¹^ORCID,Sin Sai-Weng¹^ORCID

Affiliation:

1. State Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, Faculty of Science and Technology-ECE, University of Macau, Macau, China

2. Department of Micro/Nano Electronics, Shanghai Jiao Tong University, Shanghai, China

3. Amicro Semiconductor Company Ltd., Zhuhai, China

Funder

National Key Research and Development Program of China

Science and Technology Development Fund, Macao SAR

National Natural Science Foundation of China

University of Macau

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture

Link

http://xplorestaging.ieee.org/ielx7/8919/10363413/10224293.pdf?arnumber=10224293

Reference38 articles.

1. A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation

2. A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure

3. A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS

4. A 10 bit 320 MS/s Low-Cost SAR ADC for IEEE 802.11ac Applications in 20 nm CMOS

5. A 10-bit 2.6-GS/s Time-Interleaved SAR ADC With a Digital-Mixing Timing-Skew Calibration Technique

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