A 7-bit 3.8-GS/s 2-Way Time-Interleaved 4-bit/Cycle SAR ADC 16× Time-Domain Interpolation in 28-nm CMOS-Reference-Cited by-同舟云学术

A 7-bit 3.8-GS/s 2-Way Time-Interleaved 4-bit/Cycle SAR ADC 16× Time-Domain Interpolation in 28-nm CMOS

Published:2023-09 Issue:9 Volume:70 Page:3557-3566
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Li Dengquan¹^ORCID,Zhao Xin¹^ORCID,Shen Yi¹,Liu Shubin¹^ORCID,Zhu Zhangming¹^ORCID

Affiliation:

1. Key Laboratory of Analog Integrated Circuits and Systems, Ministry of Education, School of Microelectronics, Xidian University, Xi’an, China

Funder

National Natural Science Foundation of China

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture

Link

http://xplorestaging.ieee.org/ielx7/8919/10233917/10154148.pdf?arnumber=10154148

Reference35 articles.

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2. A 29 mW 5GS/s time-interleaved SAR ADC achieving 48.5 dB SNDR with fully-digital timing-skew calibration based on digital-mixing;guo;Proc Symp VLSI Circuits,2019

3. A 7-bit 900-MS/s 2-Then-3-bit/cycle SAR ADC With Background Offset Calibration

4. A 5 GS/s 7.2 ENOB time-interleaved VCO-based ADC achieving 30.5 fJ/conv-step;baert;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2019

5. A 2.3-mW, 1-GHz, 8-Bit Fully Time-Based Two-Step ADC Using a High-Linearity Dynamic VTC

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