A TDC-assisted SAR ADC with high-speed sampling switches and fine-tuned delay cells
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Elsevier BV
Reference25 articles.
1. A 2.02–5.16 fJ/conversion step 10bit hybrid coarse-fine SAR ADC with time domain quantizer in 90 nm CMOS;Chen;IEEE J. Solid State Circ.,2016
2. A 0.3 V 10-bit 1.17 f SAR ADC with merge and split switching in 90 nm CMOS;Lin;IEEE Trans. Circuits Syst. I: Regular Papers,2015
3. A 0.6-V 13-bit 20-MS/s two-step TDC-assisted SAR ADC with PVT tracking and speed-enhanced techniques;Zhang;IEEE J. Solid State Circ.,2019
4. A 0.3V 10b 3MS/s SAR ADC with comparator calibration and kickback noise reduction for biomedical applications;Wang;IEEE Trans. Biome Circuits and Sys,2020
5. A 6-to-10-Bit 0.5 V-to-0.9 V reconfigurable 2 MS/s power scalable SAR ADC in 0.18μm CMOS;Zhu;IEEE Trans. Circuits Syst. I: Regular Papers,2015
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