An 8-bit 1.5-GS/s Voltage–Time Hybrid Two-Step ADC With Cross-Coupled Linearized VTC
Author:
Affiliation:
1. Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Microelectronics, Xidian University, Xi’an, China
Funder
National Natural Science Foundation of China
Fundamental Research Funds for the Central Universities
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Link
http://xplorestaging.ieee.org/ielx7/92/10328903/10254459.pdf?arnumber=10254459
Reference14 articles.
1. A 1GS/s 82 dB peak-SFDR 12 b single-channel pipe-SAR ADC with harmonic-injecting cross-coupled-pair and fast N-replica bootstrap switch achieving 7.5 fj/conv-step;fang;Proc IEEE Custom Integr Circuits Conf (CICC),2021
2. A 4-GS/s 39.9-dB SNDR 11.7-mW Hybrid Voltage-Time Two-Step ADC With Feedforward Ring Oscillator-Based TDCs
3. A 1.2-GS/s 8-bit Two-Step SAR ADC in 65-nm CMOS With Passive Residue Transfer
4. A 2.02–5.16 fJ/conversion step 10 bit hybrid coarse-fine SAR ADC with time-domain quantizer in 90 nm CMOS;chen;IEEE J Solid-State Circuits,2016
5. A 280MS/s 12b SAR-Assisted Hybrid ADC with Time Domain Sub-Range Quantizer in 45nm CMOS
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