A 280MS/s 12b SAR-Assisted Hybrid ADC with Time Domain Sub-Range Quantizer in 45nm CMOS-Reference-Cited by-同舟云学术

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A 280MS/s 12b SAR-Assisted Hybrid ADC with Time Domain Sub-Range Quantizer in 45nm CMOS

Published:2019-04 Issue: Volume: Page:
ISSN:
Container-title:2019 IEEE Custom Integrated Circuits Conference (CICC)
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Author:

Su Zhan,Wang Hechen,Zhao Haoyi,Chen Zhenqi,Wang Yanjie,Dai Fa Foster

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8767369/8780115/08780209.pdf?arnumber=8780209

Cited by 21 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design of a 16–bit 500 MS s^–1 SAR-ADC at 45 nm for low power and high frequency applications;Engineering Research Express;2024-02-15

2. An 8-bit 1.5-GS/s Voltage–Time Hybrid Two-Step ADC With Cross-Coupled Linearized VTC;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-12

3. A 0.4-to-0.8 V 0.1-to-5 MS/s 10 b two-step SAR ADC with TDC-based fine quantizer in 40-nm CMOS;Microelectronics Journal;2023-11

4. A 12-Bit 260-MS/s Pipelined-SAR ADC With Ring-TDC-Based Fine Quantizer for Automatic Cross-Domain Scale Alignment;IEEE Journal of Solid-State Circuits;2023-10

5. A 4.8 GS/s 11b Time-Interleaved TDC-Assisted SAR ADC with High-Speed Latch-based VTC;ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC);2023-09-11

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