A 4.8 GS/s 11b Time-Interleaved TDC-Assisted SAR ADC with High-Speed Latch-based VTC-Reference-Cited by-同舟云学术

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A 4.8 GS/s 11b Time-Interleaved TDC-Assisted SAR ADC with High-Speed Latch-based VTC

Published:2023-09-11 Issue: Volume: Page:
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Container-title:ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC)
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Author:

Deng Hao¹,Bikkina Phaneendra²,Mikkola Esko²,Zhang Runxi³,Chen Jinghong¹

Affiliation:

1. University of Houston,Houston,TX

2. Alphacore, Inc.,Tempe,AZ,USA

3. East China Normal University,Shanghai,China

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10268677/10268683/10268750.pdf?arnumber=10268750

Reference8 articles.

1. A 1-GS/s 8-Bit 12.01-fJ/conv.-step Two-Step SAR ADC in 28-nm FDSOI Technology

2. A 12 bit 100 MS/s SAR-Assisted Digital-Slope ADC

3. A 12-bit 10GS/s 16-Channel Time-Interleaved ADC with a Digital Processing Timing-Skew Background Calibration in 5nm FinFET

4. 3.3 A 5GS/s 158.6mW 12b Passive-Sampling 8×-Interleaved Hybrid ADC with 9.4 ENOB and 160.5dB FoMS in 28nm CMOS

5. A 0.97mW 260MS/s 12b Pipelined-SAR ADC with Ring-TDC-Based Fine Quantizer for PVT Robust Automatic Cross-Domain Scale Alignment

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