A 0.97mW 260MS/s 12b Pipelined-SAR ADC with Ring-TDC-Based Fine Quantizer for PVT Robust Automatic Cross-Domain Scale Alignment
Author:
Affiliation:
1. Auburn University,Auburn,AL
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9731529/9731102/09731702.pdf?arnumber=9731702
Reference5 articles.
1. A 40nm CMOS 12b 200MS/s Single-amplifier Dual-residue Pipelined-SAR ADC
2. 27.4 A 0.35mW 12b 100MS/s SAR-assisted digital slope ADC in 28nm CMOS
3. A 12-bit 210-MS/s 5.3-mW pipelined-SAR ADC with a passive residue transfer technique;lin;IEEE Symp VLSI Circuits,0
4. 3.5 A 0.6V 13b 20MS/s Two-Step TDC-Assisted SAR ADC with PVT Tracking and Speed-Enhanced Techniques
5. A 12b 330MS/s pipelined-SAR ADC with PVT-stabilized dynamic amplifier achieving <1 dB SNDR variation;huang;ISSCC,2017
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2. A 4.8 GS/s 11b Time-Interleaved TDC-Assisted SAR ADC with High-Speed Latch-based VTC;ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC);2023-09-11
3. A 400-MS/s 12-bit Voltage-Time Hybrid ADC with a Ping-Pong SAR TDC for Speed Enhancement;2023 IEEE International Symposium on Circuits and Systems (ISCAS);2023-05-21
4. A Very Low Power 12 bit 64-MS/s 2 step SAR Assisted Bidirectional Digital Slope ADC;2023 IEEE International Symposium on Circuits and Systems (ISCAS);2023-05-21
5. A 0.56-mW 63.6-dB SNDR 250-MS/s Two-Step SAR ADC in 8-nm FinFET;IEEE Solid-State Circuits Letters;2022
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