A Very Low Power 12 bit 64-MS/s 2 step SAR Assisted Bidirectional Digital Slope ADC-Reference-Cited by-同舟云学术

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A Very Low Power 12 bit 64-MS/s 2 step SAR Assisted Bidirectional Digital Slope ADC

Published:2023-05-21 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE International Symposium on Circuits and Systems (ISCAS)
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Author:

Casanova Jean-Baptiste¹,Perrin Danika¹,Nicolas Sandrine¹,Kaiser Andreas²

Affiliation:

1. STMicroelectronics,Grenoble,France

2. Univ. Lille, CNRS, Junia, Univ. Polytechnique Hauts-de-France, UMR 8520,Lille,France,F-59000

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10181241/10181318/10181656.pdf?arnumber=10181656

Reference12 articles.

1. A 0.97mW 260MS/s 12b Pipelined-SAR ADC with Ring-TDC-Based Fine Quantizer for PVT Robust Automatic Cross-Domain Scale Alignment

2. A 12 bit 100 MS/s SAR-Assisted Digital-Slope ADC

3. A 7-to-10b 0-to-4MS/s flexible SAR ADC with 6.5-to-16fJ/conversion-step

4. A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure

5. A Calibration-Free 14-b 0.7-mW 100-MS/s Pipelined-SAR ADC Using a Weighted- Averaging Correlated Level Shifting Technique

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