A 12-bit 10GS/s 16-Channel Time-Interleaved ADC with a Digital Processing Timing-Skew Background Calibration in 5nm FinFET-Reference-Cited by-同舟云学术

A 12-bit 10GS/s 16-Channel Time-Interleaved ADC with a Digital Processing Timing-Skew Background Calibration in 5nm FinFET

Published:2022-06-12 Issue: Volume: Page:
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Container-title:2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
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Author:

Moon Kyoung-Jun¹,Oh Dong-Ryeol¹,Park Young-Hyo¹,Lee Kyung-Hoon¹,Park Sun-Jae¹,Lee Sung-No¹,Hwang Hee-Chang¹,Shin Hyo-Chul¹,Cho Young-Jae¹,Choi Michael¹,Shin Jong-Shin¹

Affiliation:

1. Samsung Electronics,Hwaseong-City,South Korea

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9830116/9830138/09830208.pdf?arnumber=9830208

Reference6 articles.

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